Microelectronic devices are fabricated on a semiconductor substrate as integrated circuits in which various conductive layers are interconnected with one another to permit electronic signals to propagate within the device. An example of such a device is a complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) or MOSFET.
An exemplary FET or MOSFET includes a gate electrode on a gate dielectric layer on a surface of a silicon substrate. Recently Ge and III-V channel transistors have attracted great attention as new materials due to their high electron and hole mobility over silicon. One of the most crucial issues in establishing Ge and III-V CMOS technologies is to realize good Ge/insulator or III-V/insulator interfaces for both n- and p-MOSFETs. As with SiO2/Si, very promising results for the effective surface hole mobility using GeO2/Ge interface have been reported in p-MOSFETs. However, the use of AsOx or GeO2 interfacial layers and deposited high-k dielectric materials has not provided high electron mobility n-MOSFETs, due to chemical and thermal instabilities of AsOx and GeO2, as well as the high trap density near the conduction band of the Ge or III-V, which results in electron scattering and lower electron mobility.
Therefore, there is a need for new interfacial layers between Ge or III-V materials and high-k dielectrics, as well as methods and apparatus for forming such layers.